1. Field of the Invention
The present invention generally relates to semiconductor memory circuits, and more particularly to a semiconductor memory circuit which operates in synchronism with a clock signal.
Nowadays, a central processing unit (CPU) operates at a high speed, and a semiconductor circuit such as a dynamic random access memory (DRAM) is thus required to perform a data input/output operation at a high frequency and speed up a data transfer. As semiconductor memory circuits capable of satisfying such a requirement, there are known a synchronous dynamic random access memory (SDRAM) and a fast cycle random access memory (FCRAM), which memories operate in synchronism with a clock signal supplied from the outside of the circuits.
However, the above semiconductor circuits tend to need an increased chip area in accordance with an increase in the circuit scale and the memory capacity due to the speeding up of the data transfer speed. Hence, it is required to provide a semiconductor memory circuit having a reduced chip area without decreasing the memory capacity.
2. Description of the Prior Art
A description will now be given of a conventional semiconductor memory circuit such as a DRAM.
FIG. 1 is a block diagram of a conventional semiconductor memory circuit, which includes memory cell arrays 201-208, and sense amplifier groups 209-212. The memory cell arrays 201-208 are arranged in rows and columns in a matrix formation. In the circuit shown in FIG. 1, eight memory cell arrays 201-208 are arranged in two rows and four columns. The sense amplifier groups 209-212 receive and hold data read from memory cells selected by main word decoders MWD and sub word decoders SWD. Further, the memory circuit has redundant cells 213a-213d and 214a-214d respectively associated with the memory cell arrays 201-208, and is thus saved from a fault such as a fault of a memory cell or a defect of a column select signal. Each of the memory cell arrays 201-208 has memory cells arrayed in a matrix formation of 16 rows and 4 columns.
FIG. 2 is an enlarged block diagram of the part of the memory circuit indicated by a broken-line circle shown in FIG. 1. In FIG. 2, S/A denotes a sense amplifier, CL denotes a column select line, DB_SW denotes a data bus switch, MWL denotes a main word line, SWL denotes a sub word line, GDB00X,Z denotes a pair of global data bus lines, and b11x,z and b12x,z denote pairs of bit lines.
All the memory cell arrays in the column direction selected by the main word line MWL extending from the main word decoder MWD are enabled. In FIG. 1, such all the memory cell arrays are illustrated with hatching. Then, the sub word line extending from one of the sub word decoders SWD is enabled, and data stored in the memory cells connected to the enabled memory cells are output to the corresponding sense amplifiers S/A. The data sensed and held by the sense amplifiers S/A are read from the sense amplifiers selected by the column select line CL, and are then output to the outside of the memory circuit via the (local) data bus DB, the data bus switch DB_SW, and the global data bus GDB00X,Z. If there is a fault in the data bus related to the memory cell array which is enabled, for example, the memory cell array 201, the defective column select line corresponding to the fault is replaced by a redundant column select line for selecting the redundant cell 213a. Thus, the circuit can be saved from the fault.
However, the arrangement shown in FIGS. 1 and 2 does not allow a large number of pairs of global data bus lines along the sides of the memory cell arrays. The above fact does not satisfy a high-speed, multiple-bit data outputting requirement. Further, all the memory cell arrays in the column direction are all enabled at once by the main word line MWL, which is thus burdened heavily. If a power supply voltage drops, the circuit will be forced to operate at a reduced speed.
With the above in mind, an improved semiconductor memory circuit has been proposed in which the memory cell arrays are designed to have a reduced size, and a reduced number of memory cells is activated at one time. In other words, such an improved memory circuit has main word lines arranged in a distributed fashion.
FIG. 3 is a block diagram of such an improved semiconductor memory circuit capable of outputting data in a multiple-bit formation. The circuit shown in FIG. 3 includes 16 memory cell arrays 221-236 arranged in four rows and four columns, and sense amplifier groups 237-240 which receive and hold data from memory cells selected by the main word decoder MWD and the sub word decoders SWD. Further, redundant memory cells 241a-241d, 242a-242d, 243a-243d, and 244a-244d are respectively provided to the memory cell arrays 221-236. Each of the memory cell arrays 221-236 includes memory cells arrayed in eight rows and four columns. That is, the number of memory cells provided in each of the memory cell arrays 221-236 is half that of memory cells provided in each of the memory cell arrays 201-208 shown in FIG. 1.
As shown in FIG. 3, four memory cell arrays 221, 226, 231 and 236 illustrated with hatching and located in mutually different row and columns are all enabled at once by four main word lines extending from the main word decoder MWD. Then, data stored in all memory cells selected by the sub word lines extending from the sub word decoders SWD are output to the sense amplifiers. The data latched in the sense amplifiers are read from sense amplifiers selected by the column select lines CL extending along the sides of the memory cell arrays, and are then output to the outside of the circuit via the data bus provided on the memory cell arrays. If a fault exists in one of the memory cell arrays which are enabled, for example, the memory cell array 221, the defective column select line corresponding to the related data is replaced by a column select line for selecting the redundant cell 241a. Thus, the circuit can be saved from the fault.
As described above, each memory cell array has a reduced size and the main word lines extending from the main word decoder are respectively provided to the columns. Hence, each of the main word lines has a reduced load. The redundant memory cells are respectively provided to the memory cell arrays 221-236, so that the redundant efficiency can be improved.
However, the semiconductor memory circuit shown in FIG. 3 needs a large chip size because the redundant memory cells are respectively provided to the memory cell arrays 221-236. Hence, a very large chip area is needed to increase the memory capacity.
It is a general object of the present invention to provide a semiconductor memory circuit in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a semiconductor memory circuit having a reduced chip size without degrading the redundant efficiency.
The above objects of the present invention are achieved by a semiconductor memory circuit comprising the following. A plurality of memory cell arrays are arranged in rows and columns. A decoder circuit selects a predetermined number of memory cell arrays from among the plurality of the memory cell arrays. Sense amplifiers sense data read from selected memory cell arrays. The plurality of memory cell arrays are grouped into a first type of memory cell arrays each having a redundant memory cell and a second type of memory cell arrays each having no redundant memory cell.
The above objects of the present invention are also achieved by a semiconductor memory circuit including the following. A plurality of memory cell arrays are arranged in rows and columns. A decoder circuit selects a predetermined number of memory cell arrays from among the plurality of the memory cell arrays. Sense amplifiers sense data read from selected memory cell arrays. Redundant memory cell arrays are respectively provided to the rows.